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1. general description the p89lpc970/971/972 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architec ture that executes instructions in two to four clocks, six times the rate of standard 80c51 devices. many s ystem-level functions have been incorporated into the p89lpc970/971/972 in order to reduce component count, board space, and system cost. 2. features and benefits 2.1 principal features ? 2 kb/4 kb/8 kb byte-erasable flash code memory organized into 1 kb sectors and 64-byte pages. single-byte erasing allows any byte(s) to be used as non-volatile data storage. ? 256-byte ram data memory. ? two analog comparators with selectable inputs and reference source. ? five 16-bit counter/timers (each may be conf igured to toggle a port output upon timer overflow or to become a pwm output). ? a 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. ? enhanced uart with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 khz byte-wide i 2 c-bus communication port. ? spi communication port (pin remap). ? high-accuracy internal rc oscilla tor option 7.373 mhz calibrated to 1 %, with clock doubler option, allows oper ation without external osc illator components. the rc oscillator option is select able and fine tunable. ? watchdog timer with separate on- chip oscillator, nominal 40 0 khz/25 khz, calibrated to 10 % at 400 khz, requiring no external components. the watchdog prescaler is selectable from eight values. ? pin remap for uart, i 2 c-bus and spi. ? 2.4 v to 5.5 v v dd operating range. ? enhanced low voltage (brown out) detect allows a graceful system shutdown when power fails. ? 20-pin tssop and dip packa ges with 15 i/o pins minimum and up to 18 i/o pins while using on-chip osc illator and re set options. p89lpc970/971/972 8-bit microcontroller with accel erated two-clock 80c51 core 2 kb/4 kb/8 kb wide-voltage byte-erasable flash rev. 3 ? 8 june 2010 product data sheet
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 2 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 2.2 additional features ? a high performance 80c51 cpu provides inst ruction cycle times of 111 ns to 222 ns for all instructions except multiply and divi de when executing at 18 mhz. this is six times the performance of the standard 80c5 1 running at the same clock frequency. a lower clock frequency for the same performance results in power savings and reduced emi. ? serial flash in-circuit programming (icp ) allows simple production coding with commercial eprom programmers. flash security bits prevent reading of sensitive application programs. ? serial flash in-system programming (isp) a llows coding while the device is mounted in the end application. ? in-application programming (iap) of the flash code memory. this allows changing the code in a running application. ? clock switching on the fly amon g internal rc oscillator, wa tchdog oscillator, external clock source provides opti mal support of minimal powe r active mode with fast switching to maximum performance. ? idle and two different power-down reduced power modes. improved wake-up from power-down mode (a low interrupt input starts execution). typical power-down current is 1 a (total power-down with voltage comparators disabled). ? integrated pmu (power management unit) automatically adjusts internal regulators to minimize power consumption during idle mode, power-down mode and total power-down mode. in addition, the power consumption can be further reduced in normal or idle mode through configuring regulators modes according to the applications. ? active-low reset. on-chip power-on reset allows operation without external reset components. a software reset function is also available. ? configurable on-chip oscilla tor with frequency range op tions selected by user programmed flash configurat ion bits. oscillator options support frequencies from 20 khz to the maximum operating frequency of 18 mhz. ? oscillator fail detect. the watchdog timer has a separate fully on-chip oscillator allowing it to perform an os cillator fail detect function. ? programmable port output configuration opti ons: quasi-bidirectional, open drain, push-pull, input-only. ? high current sourcing/sinking (20 ma) on ei ght i/o pins (p0.3 to p0.7, p1.4, p1.6, p1.7). all other port pins have high si nking capability (20 ma). a maximum limit is specified for the entire chip. ? port ?input pattern match? detect. port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. ? controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. ? only power and ground connections are required to operate the p89lpc970/971/972 when internal reset option is selected. ? four interrupt pr iority levels. ? eight keypad interrupt inputs, plus two additional external interrupt inputs. ? schmitt trigger port inputs. ? second data pointer. ? emulation support.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 3 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version p89lpc970fdh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 p89lpc971fdh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 p89lpc972fdh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 p89lpc972fn dip20 plastic dual in-line package; 20 leads (300 mil) sot146-1 table 2. ordering options type number flash memory temperature range frequency p89lpc970fdh 2 kb ? 40 cto+85 c 0mhzto18mhz p89lpc971fdh 4 kb ? 40 cto+85 c 0mhzto18mhz p89lpc972fdh 8 kb ? 40 cto+85 c 0mhzto18mhz p89lpc972fn 8 kb ? 40 cto+85 c 0mhzto18mhz
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 4 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 4. block diagram (1) for pin remap fig 1. block diagram accelerated 2-clock 80c51 cpu 2 kb/4 kb/8 kb code flash 256-byte data ram port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock configurable oscillator on-chip rc oscillator with clock doubler internal bus power management (power-on reset, brownout reset, regulators) 002aae550 uart analog comparators i 2 c-bus port 3 configurable i/os p89lpc970/971/972 watchdog timer and oscillator timer 0 timer 1 real-time clock/ system timer spi p3[1:0] p1[7:0] p0[7:0] txd rxd scl sda t0 t1 cmp2 cin2b cin2a cmp1 cin1a cin1b timer 2 timer 3 timer 4 t2 t2ex t3 t3ex t4 t4ex spiclk (1) mosi (1) miso (1) ss (1) crystal or resonator xtal2 xtal1
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 5 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 5. functional diagram (1) for pin remap fig 2. functional diagram v dd v ss port 0 port 3 txd rxd t0 int0 int1 rst scl sda 002aae551 cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 t1 xtal2 xtal1 spiclk (1) t2 kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 kbi6 kbi7 t3 port 1 t2ex t4 t4ex ss (1) mosi (1) miso (1) t3ex p89lpc970/ 971/972 clkout
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 6 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 6. pinning information 6.1 pinning fig 3. tssop20 pin configuration fig 4. p89lpc972 dip20 pin configuration p89lpc970/971/972 p0.0/cmp2/kbi0/spiclk p0.1/cin2b/kbi1 p1.7/t3ex/mosi p0.2/cin2a/kbi2 p1.6/miso p0.3/cin1b/kbi3/t2 p1.5/rst p0.4/cin1a/kbi4 v ss p0.5/cmpref/kbi5/t3 p3.1/xtal1 v dd p3.0/xtal2/clkout p0.6/cmp1/kbi6 p1.4/int1/t4ex/ss p0.7/kbi7/t1 p1.3/int0/sda/t4 p1.0/txd p1.2/scl/t0 p1.1/rxd/t2ex 002aae552 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 p0.0/cmp2/kbi0/spiclk p1.7/t3ex/mosi p1.6/miso v ss p3.1/xtal1 p3.0/xtal2/clkout p1.4/int1/t4ex/ss p1.3/int0/sda/t4 p1.2/scl/t0 002aae553 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 p1.5/rst p0.1/cin2b/kbi1 p0.2/cin2a/kbi2 p0.3/cin1b/kbi3/t2 p0.4/cin1a/kbi4 p0.5/cmpref/kbi5/t3 v dd p0.6/cmp1/kbi6 p0.7/kbi7/t1 p1.0/txd p1.1/rxd/t2ex p89lpc972
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 7 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 6.2 pin description table 3. pin description symbol pin type description dip20, tssop20 p0.0 to p0.7 i/o port 0: port 0 is an 8-bit i/o port with a user-c onfigurable output type. during reset port 0 latches are configured in the inpu t-only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to section 7.16.1 ? port configurations ? and ta b l e 11 ? static characteristics ? for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt trigger inputs. port 0 also provides various special functions as described below: p0.0/cmp2/kbi0/ spiclk 1i/o p0.0 ? port 0 bit 0. o cmp2 ? comparator 2 output i kbi0 ? keyboard input 0. i/o spiclk ? spi clock. when configured as ma ster, this pin is output; when configured as slave, this pin is input (pin remap). p0.1/cin2b/ kbi1 20 i/o p0.1 ? port 0 bit 1. i cin2b ? comparator 2 positive input b. i kbi1 ? keyboard input 1. p0.2/cin2a/ kbi2 19 i/o p0.2 ? port 0 bit 2. i cin2a ? comparator 2 positive input a. i kbi2 ? keyboard input 2. p0.3/cin1b/ kbi3/t2 18 i/o p0.3 ? port 0 bit 3. high current source. i cin1b ? comparator 1 positive input b. i kbi3 ? keyboard input 3. i/o t2 ? timer/counter 2 external count input or overflow output. p0.4/cin1a/ kbi4 17 i/o p0.4 ? port 0 bit 4. high current source. i cin1a ? comparator 1 positive input a. i kbi4 ? keyboard input 4. p0.5/cmpref/ kbi5/t3 16 i/o p0.5 ? port 0 bit 5. high current source. i cmpref ? comparator reference (negative) input. i kbi5 ? keyboard input 5. i/o t3 ? timer/counter 3 external count input or overflow output.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 8 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core p0.6/cmp1/kbi6 14 i/o p0.6 ? port 0 bit 6. high current source. o cmp1 ? comparator 1 output. i kbi6 ? keyboard input 6. p0.7/kbi7/t1 13 i/o p0.7 ? port 0 bit 7. high current source. i kbi7 ? keyboard input 7. i/o t1 ? timer/counter 1 external count input or overflow output. p1.0 to p1.7 i/o, i [1] port 1: port 1 is an 8-bit i/o port with a us er-configurable output type, except for three pins as noted below. during reset port 1 latches are configured in the input-only mode with the internal pull-up di sabled. the operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. each of the configurable port pins ar e programmed independently. refer to section 7.16.1 ? port configurations ? and ta b l e 11 ? static characteristics ? for details. p1.2 to p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt trigger inputs. port 1 also provides various special functions as described below: p1.0/txd 12 i/o p1.0 ? port 1 bit 0. o txd ? transmitter output for serial port. p1.1/rxd/t2ex 11 i/o p1.1 ? port 1 bit 1. i rxd ? receiver input for serial port. i t2ex ? timer/counter 2 external capture input. p1.2/scl/t0 10 i/o p1.2 ? port 1 bit 2 (open-drain when used as output). i/o scl ? i 2 c-bus serial clock input/output. i/o t0 ? timer/counter 0 external count input or overflow output. (open-drain when used as output.) p1.3/int0 /sda/ t4 9i/o p1.3 ? port 1 bit 3 (open-drain when used as output). i int0 ? external interrupt 0 input. i/o sda ? i 2 c-bus serial data input/output. i/o t4 ? timer/counter 4 external count input or overflow output. p1.4/int1 /t4ex/ ss 8i/o p1.4 ? port 1 bit 4. high current source. i int1 ? external interrupt 1 input. i t4ex ? timer/counter 4 external capture input. i ss ? spi slave select i nput (pin remap). p1.5/rst 4i p1.5 ? port 1 bit 5 (input only). i rst ? external reset input during power-on or if selected via ucfg1. when functioning as a reset input, a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. also used duri ng a power-on sequence to force isp mode. p1.6/miso 3 i/o p1.6 ? port 1 bit 6. high current source. i/o miso ? spi master in slave out. when config ured as master, this pin is input, when configured as slave, this pin is output (pin remap). table 3. pin description ?continued symbol pin type description dip20, tssop20
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 9 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core [1] input/output for p1.0 to p1.4, p1.6, p1.7. input for p1.5. p1.7/t3ex/mosi 2 i/o p1.7 ? port 1 bit 7. high current source. i t3ex ? timer/counter 3 external capture input. i/o mosi ? spi master out slave in. when configur ed as master, this pin is output; when configured as slave, this pin is input (pin remap). p3.0 to p3.1 i/o port 3: port 3 is a 2-bit i/o port with a user-configurable output type. during reset port 3 latches are configured in the inpu t-only mode with the internal pull-up disabled. the operation of port 3 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to section 7.16.1 ? port configurations ? and ta b l e 11 ? static characteristics ? for details. all pins have schmitt trigger inputs. port 3 also provides various special functions as described below: p3.0/xtal2/ clkout 7i/o p3.0 ? port 3 bit 0. o xtal2 ? output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration. o clkout ? cpu clock divided by 2 when enabled via sfr bit (enclk -trim.6). it can be used if the cpu clock is the internal rc oscillator, watchdog oscillator or external clock input, except when xtal1/xtal2 are used to generate clock source for the rtc/system timer. p3.1/xtal1 6 i/o p3.1 ? port 3 bit 1. i xtal1 ? input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). it can be a port pin if internal rc oscillator or watchdog oscillator is used as the cpu clock source, and if xtal1/xtal2 are not used to generate the clo ck for the rtc/system timer. v ss 5i ground: 0 v reference. v dd 15 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 3. pin description ?continued symbol pin type description dip20, tssop20
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 10 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7. functional description remark: please refer to the p89lpc970/971/972 user manual for a more detailed functional description. 7.1 special function registers remark: sfr accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not defined. ? accesses to any defined sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled ?-?, ?0? or ?1? can only be written and read as follows: ? ?-? unless otherwise specified, must be written with ?0?, but can return any value when read (even if it was wr itten with ?0?). it is a reserved bit and may be used in future derivatives. ? ?0? must be written with ?0?, and will return a ?0? when read. ? ?1? must be written with ?1?, and will return a ?1? when read.
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 11 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core table 4. special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 0000 000 0 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 0000 00x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 0000 000 0 brgr0 [1] baud rate generator 0 rate low beh 00 0000 000 0 brgr1 [1] baud rate generator 0 rate high bfh 00 0000 000 0 brgco n baud rate generator 0 control bdh - - - - - - sbrgs brgen 00 [1] xxxx xx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00 [2] xx00 0000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [2] xx00 0000 divm cpu clock divide-by-m control 95h 00 0000 000 0 dptr data pointer (2 bytes) dph data pointer high 83h 00 0000 000 0 dpl data pointer low 82h 00 0000 000 0 fmadrh program flash address high e7h 00 0000 000 0 fmadrl program flash address low e6h 00 0000 000 0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 12 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 0111 0000 program flash control (write) e4h fmcmd. 7 fmcmd. 6 fmcmd. 5 fmcmd. 4 fmcmd. 3 fmcmd. 2 fmcmd. 1 fmcmd. 0 fmdata program flash data e5h 00 0000 000 0 i2adr i 2 c-bus slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 0000 000 0 bit address df de dd dc db da d9 d8 i2con* i 2 c-bus control register d8h - i2en sta sto si aa - crsel 00 x000 00x0 i2dat i 2 c-bus data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 0000 000 0 i2scll serial clock generator/scl duty cycle register low dch 00 0000 000 0 i2stat i 2 c-bus status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 1111 1000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 0000 000 0 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h - est - extim espi ec ekbi ei2c 00 [2] 00x0 0000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [2] x000 0000 ip0h interrupt priority 0 high b7h - pwdrth pboh psh/ psrh pt1h px1h pt0h px0h 00 [2] x000 0000 table 4. special function registers ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 13 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h - pst - pxtim pspi pc pkbi pi2c 00 [2] 00x0 0000 ip1h interrupt priority 1 high f7h - psth - pxtimh pspih pch pkbih pi2ch 00 [2] 00x0 0000 kbcon keypad control register 94h------patn _sel kbif 00 [2] xxxx xx00 kbmask keypad interrupt mask register 86h 00 0000 000 0 kbpatn keypad pattern register 93h ff 1111 1111 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h t1/kb7 cmp1/ kb6 cmpref / kb5/t3 cin1a/ kb4 cin1b/ kb3/t2 cin2a/ kb2 cin2b/ kb1 cmp2/ kb0 [2] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h t3ex - rst int1 / t4ex int0 / sda/t4 t0/scl rxd/ t2ex txd [2] bit address b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h - - - - - - xtal1 xtal2 [2] p0m1 port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1 .5) (p0m1.4) (p0m1.3) (p0m1 .2) (p0m1.1) (p0m1.0) ff [2] 1111 1111 p0m2 port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2 .5) (p0m2.4) (p0m2.3) (p0m2 .2) (p0m2.1) (p0m2.0) 00 [2] 0000 000 0 p1m1 port 1 output mode 1 91h (p1m1.7) (p1m1.6) - (p1m1.4) (p1m 1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [2] 11x1 xx11 p1m2 port 1 output mode 2 92h (p1m2.7) (p1m2.6) - (p1m2.4) (p1m 2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [2] 00x0 xx00 p3m1 port 3 output mode 1 b1h - - - - - - (p3m1.1) (p3m1.0) 03 [2] xxxx xx11 p3m2 port 3 output mode 2 b2h - - - - - - (p3m2.1) (p3m2.0) 00 [2] xxxx xx00 table 4. special function registers ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 14 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core pcon power control register 87h smod1 smod0 - boi gf1 gf0 pmod1 pmod0 00 0000 000 0 pcona power control register a b5h rtcpd - vcpd - i2pd sppd spd - 00 [2] 0000 000 0 pincon pin remap control register cfh------spi-00 [2] 0000 000 0 pmuco n power management unit control register fah lpmod - - - - - - hcok 0xxx xxx1 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 0000 000 0 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00 000x pwmd2 h pwm free cycle register 2 high byte aeh 00 0000 0000 pwmd2l pwm free cycle register 2 low byte afh 00 0000 0000 pwmd3 h pwm free cycle register 3 high byte e9h 00 0000 0000 pwmd3l pwm free cycle register 3 low byte eah 00 0000 0000 pwmd4 h pwm free cycle register 4 high byte aah 00 0000 0000 pwmd4l pwm free cycle register 4 low byte abh 00 0000 0000 rcap2h capture register 2 high byte fch 00 0000 0000 table 4. special function registers ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 15 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core rcap2l capture register 2 low byte fbh 00 0000 0000 rcap3h capture register 3 high byte ech 00 0000 0000 rcap3l capture register 3 low byte ebh 00 0000 0000 rcap4h capture register 4 high byte cah 00 0000 0000 rcap4l capture register 4 low byte c9h 00 0000 0000 rstsrc reset source register dfh - boif borf pof r_kb r_wd r_sf r_ex [3] rtccon rtc control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [2] [4] 011x xx00 rtch rtc register high d2h 00 [4] 0000 000 0 rtcl rtc register low d3h 00 [4] 0000 000 0 saddr serial port address register a9h 00 0000 000 0 saden serial port address enable b9h 00 0000 000 0 sbuf serial port data buffer register 99h xx xxxx xxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 0000 000 0 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 0000 000 0 sp stack pointer 81h 07 0000 0111 spctl spi control register e2h ssig spen dord mstr cpol cpha spr1 spr0 04 0000 010 0 table 4. special function registers ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 16 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core spstat spi status register e1h spif wcol - - - - - - 00 00xx xxxx spdat spi data register e3h 00 0000 000 0 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0 xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 0000 000 0 th0 timer 0 high 8ch 00 0000 000 0 th1 timer 1 high 8dh 00 0000 000 0 tl0 timer 0 low 8ah 00 0000 000 0 tl1 timer 1 low 8bh 00 0000 000 0 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 0000 0000 t2con timer/counter 2 control ffh psel2 ent2 tien2 pwm2 exen2 t r2 c/nt2 cp/nrl2 00 0000 000 0 th2 timer/counter 2 high byte feh 00 0000 000 0 tl2 timer/counter 2 low byte fdh 00 0000 0000 t3con timer/counter 3 control efh psel3 ent3 tien3 pwm3 exen3 tr3 c/nt3 cp/nrl3 00 0000 000 0 th3 timer/counter 3 high byte eeh 00 0000 000 0 tl3 timer/counter 3 low byte edh 00 0000 0000 t4con timer/counter 2 control cdh psel4 ent4 tien4 pwm4 exen4 tr4 c/nt4 cp/nrl4 00 0000 000 0 table 4. special function registers ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 17 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core [1] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpre dictable. [2] all ports are in input only (high-impedance) state after power-up. [3] the rstsrc register reflects the caus e of the p89lpc970/971/972 reset except boif bit. upon a power-up reset, all reset sour ce flags are cleared except pof and bof; the power-on reset value is x011 0000. [4] the only reset sources that affect these sfrs are power-on reset and watchdog reset. [5] on power-on reset and watchdog reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initialization of the trim register. [6] after reset, the value is 1110 01x1, i.e., pre2 to pre0 are all logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watc hdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. th4 timer/counter 4 high byte cch 00 0000 000 0 tl4 timer/counter 4 low byte cbh 00 0000 0000 tintf timer/counters 2/3/4 overflow and external flags ceh - - tf4 exf4 tf3 exf3 tf2 exf2 00 0000 000 0 trim internal oscillator trim register 96h rcclk enclk trim.5 trim.4 t rim.3 trim.2 trim.1 trim.0 [4] [5] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 1111 1111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 4. special function registers ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 18 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core [1] extended sfrs are physically located on-chi p but logically located in external data memory address space (xdata). the movx a ,@dptr and movx @dptr,a instructions are used to access these extended sfrs. [2] the boicfg2/1/0 will be copied from ucfg1.5 to ucfg1.3 when power-on reset. [3] clkcon register reset value comes from ucfg1. the reset value of clkcon.2 to clkcon.0 come from ucfg1.2 to ucfg1.0 and reset value of clkdbl bit comes from ucfg1.7. table 5. extended special function registers [1] name description sfr addr. bit functions and addresses reset value msb lsb hex binary bodcfg bod configuration register ffc8h - - - - - boicfg2 boicfg1 boicfg0 [2] clkcon clock control register ffdeh clkok - wdmod xtalwd clkdbl fosc2 fosc1 fosc0 [3] 1000 xxxx cmpref comparator reference register ffcbh - refs5 refs4 refs3 - refs2 refs1 refs0 00 0000 0000 rtcdat h real-time clock data register high ffbfh 00 0000 0000 rtcdatl real-time clock data register low ffbeh 00 0000 0000
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 19 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.2 enhanced cpu the p89lpc970/971/972 uses an enhanced 80c51 cpu which runs at six times the speed of standard 80c51 devices. a machine cycle consists of two cpu clock cycles, and most instructions execute in one or two machine cycles. 7.3 clocks 7.3.1 clock definitions the p89lpc970/971/972 device has several internal clocks as defined below: oscclk ? input to the divm clock divider. oscclk is selected from one of four clock sources (see figure 5 ) and can also be optionally divided to a slower frequency (see section 7.11 ? cclk modification: divm register ? ). remark: f osc is defined as the oscclk frequency. cclk ? cpu clock; output of the clock divider. there are two cclk cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four cclk cycles). rcclk ? the internal 7.373 mhz rc oscillator ou tput. the clock doubler option, when enabled, provides an output frequency of 14.746 mhz. pclk ? clock for the various peripheral devices and is cclk 2 . 7.3.2 cpu clock (oscclk) the p89lpc970/971/972 pr ovides several user-selectable o scillator options in generating the cpu clock. this allows optimization for a range of needs from high precision to lowest possible cost. these options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip rc oscillator, an oscillator using an external crystal, or an external clock source. 7.4 crystal oscillator option the crystal oscillator option can be optimized for low, medium, or high frequency crystals covering a range from 20 khz to 18 mhz. it can be the clock source of oscclk and rtc. the low speed oscillator option can be the cloc k source of the wdt. 7.4.1 low speed oscillator option this option supports an external crystal in the range of 20 khz to 100 khz. ceramic resonators are also supported in this configuration. 7.4.2 medium speed oscillator option this option supports an external crystal in the range of 100 khz to 4 mhz. ceramic resonators are also supported in this configuration. 7.4.3 high speed oscillator option this option supports an external crystal in the range of 4 mhz to 18 mhz. ceramic resonators are also supported in this configuration.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 20 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.5 clock output the p89lpc970/971/972 supports a user-sel ectable clock output function on the p3.0/xtal2/clkout pin when cryst al oscillator is not being us ed. this condition occurs if another clock source has been selected (on-chip rc oscilla tor, watchdog oscillator, external clock input on xtal1) and if the rt c and wdt are not using the crystal oscillator as their clock source. this allows ex ternal devices to synchronize to the p89lpc970/971/972. this output is enabled by the enclk bit in the trim register. the frequency of this clock output is 1 2 that of the cclk. if th e clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. 7.6 on-chip rc oscillator option the p89lpc970/971/972 has a 6-bit trim re gister that can be used to tune the frequency of the rc oscillator. during reset, the trim value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 mhz 1 % at room temperature. end-user applications can write to the trim register to adjust the on-chip rc oscillator to other frequencies. when the cl ock doubler option is enabled (ucfg2.7 = 1), the output frequency is 14.746 mhz. if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to logic 1 to reduce power consumption. on reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower. when clock doub ler option is enabled, boe0 to boe2 bits (ucfg1[3:5]) are r equired to hold the device in reset at power-up until v dd has reached its specified level. 7.7 watchdog oscillator option the watchdog has a sepa rate oscillator which provides two options: 400 khz and 25 khz. it is calibrated to 10 % at 400 khz. the oscillator can be used to save power when a high clock frequency is not needed. 7.8 external clock input option in this configuration, the processor clock is derived from an external source driving the p3.1/xtal1 pin. the rate may be from 0 hz up to 18 mhz. the p3.0/xtal2/clkout pin may be used as a standard port pin or a clock output. when using an oscillator frequency above 12 mhz, boe0 to boe2 bits (ucfg1[3:5]) are required to hold the device in reset at power-up until v dd has reached its specified level. 7.9 clock source switching on the fly p89lpc970/971/972 can implement clock s witching on any sources of watchdog oscillator, 7 mhz/14 mhz internal rc oscillator, crystal os cillator and exter nal clock input during code is running. clkok bit in clkcon re gister is used to indicate the clock switch status. clkok is cleared when starting cloc k source switch and set when completed. notice that when clkok is ?0?, writin g to clkcon register is not allowed.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 21 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.10 cclk wake-up delay the p89lpc970/971/972 has an internal wake -up timer that delays the clock until it stabilizes depending on the clock source used. if the clock source is any of the three crystal selections (low, medium and high fr equencies) the delay is 1024 oscclk cycles plus 60 sto100 s. if the clock source is the inter nal rc oscillator, the delay is 200 s to 300 s. if the clock source is watchdog osc illator or external cl ock, the delay is 32 oscclk cycles. 7.11 cclk modificati on: divm register the oscclk frequency can be divided down up to 510 times by configuring a dividing register, divm, to generate ccl k. this feature makes it poss ible to temporarily run the cpu at a lower rate, reducing power consumption. by dividing the clock, the cpu can retain the ability to respond to events that would not exit idle mode by executing its normal program at a lower rate. this can also allow by passing the oscillator start-up time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time with out interrupting code execution. 7.12 low power select the p89lpc970/971/972 is designed to run at 18 mhz (cclk) maximum. however, if cclk is 8 mhz or slower, the clklp sfr bit (a uxr1.7) can be set to logic 1 to lower the power consumption further. on any reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower. (1) 10 % at 400 khz. fig 5. block diagram of oscillator control 2 002aae554 rtc cpu wdt divm cclk uart oscclk timer 2/ timer 3/ timer 4 pclk timer 0/ timer 1 high frequency medium frequency low frequency xtal1 xtal2 rc oscillator with clock doubler watchdog oscillator (7.3728 mhz/14.7456 mhz 1 %) pclk rcclk spi (1) i 2 c-bus (400 khz/25 khz 10 %)
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 22 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.13 memory organization the various p89lpc970/971/972 memory spaces are as follows: ? data 128 bytes of internal data memory space (00h:7fh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? idata indirect data. 256 bytes of internal da ta memory space (00h:ffh) accessed via indirect addressing using instructions othe r than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 bytes immediately above it. ? sfr special function registers. selected cpu re gisters and peripheral control and status registers, accessible only via direct addressing. ? xdata ?external? data or au xiliary ram. duplicates the cl assic 80c51 64 kb memory space addressed via the movx instruction using th e dptr, r0, or r1. all or part of this space could be implemented on-chip. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the p89lpc970/971/972 has 4 kb/8 kb of on-chip code memory. 7.14 data ram arrangement the 768 bytes of on-chip ram are organized as shown in ta b l e 6 . 7.15 interrupts the p89lpc970/971/972 uses a four priority le vel interrupt structure. this allows great flexibility in controlling the handling of the many interr upt sources. the p89lpc970/971/972 supports 15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, timer 2/3/4, serial port tx, serial port rx, combined serial port rx/tx, brownout detect, watchdog/rtc, i 2 c-bus, keyboard, comparators 1 and 2, spi. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts. each interrupt source can be individually pr ogrammed to one of four priority levels by setting or clearing bits in the interrupt priority registers ip0, ip0h, ip1 and ip1h. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but table 6. on-chip data memory usages type data ram size (bytes) data memory that can be address ed directly and indirectly 128 idata memory that can be addressed indirectly 256 xdata auxiliary (external data) on-chip memory that is accessed using the movx instructions 256
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 23 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt so urce. if two requests of different priority levels are pending at the start of an instructio n, the request of higher priority level is serviced. if requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve pending requests of the same priority level. 7.15.1 external interrupt inputs the p89lpc970/971/972 has two external interrupt inputs as well as the keypad interrupt function. the two interrupt inputs are identical to those present on the standard 80c51 microcontrollers. these external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit it1 or it0 in register tcon. in edge-triggered mode, if successive samples of the intn pin show a high in one cycle and a low in the next cycle, the interrupt request flag ien in tcon is set, causing an interrupt request. if an external interrupt is enabled when the p89lpc970/971/972 is put into power-down or idle mode, the interrupt will cause the processor to wake -up and resume operation. refer to section 7.17.3 ? power reduction modes ? for details.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 24 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core (1) for pin remap. fig 6. interrupt sources, interrupt enables, and power-down wake-up sources 002aae555 ie0 ex0 ie1 ex1 boif ebo kbif ekbi interrupt to cpu wake-up (if in power-down) ewdrt cmf2 cmf1 ec ea (ie0.7) tf1 et1 ti and ri/ri es/esr ti est si ei2c spif (1) espi (1) rtcf ertc wdovf tf0 et0 tf2 exf2 tien4 extim tien2 tf3 exf3 tien3 tf4 exf4
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 25 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.16 i/o ports the p89lpc970/971/972 has four i/o ports: port 0, port 1 and port 3. ports 0, 1 are 8-bit ports, and port 3 is a 2-bit port. the exact nu mber of i/o pins ava ilable depends upon the clock and reset options chosen, as shown in ta b l e 7 . 7.16.1 port configurations all but three i/o port pins on the p89lpc970/971/972 may be configured by software to one of four types on a bit-by-bit basis. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input-on ly. two configuration registers for each port select the output type for each port pin. 1. p1.5/rst can only be an input and cannot be configured. 2. p1.2/scl/t0 and p1.3/int0 /sda/t4 may only be configured to be either input-only or open-drain. 7.16.1.1 quasi-bidirectional output configuration quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. this is possible beca use when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is driven low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. a quasi-bidirectional port pin has a schmitt tri gger input that also has a glitch suppression circuit. 7.16.1.2 open-drain output configuration the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port la tch contains a logic 0. to be used as a logic output, a port configured in this manner must ha ve an external pull-up, typically a resistor tied to v dd . an open-drain port pin has a schmitt trigger input that also has a glitch suppression circuit. table 7. number of i/o pins available clock source reset option number of i/o pins (20-pin package) on-chip oscillator or watchdog oscillator no external reset (except during power-up) 18 external rst pin supported 17 external clock input no external reset (except during power-up) 17 external rst pin supported 16 low/medium/high speed oscillator (external crystal or resonator) no external reset (except during power-up) 16 external rst pin supported 15
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 26 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.16.1.3 input-only configuration the input-only port configuration has no output drivers. it is a schm itt trigger input that also has a glitch suppression circuit. 7.16.1.4 push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. a push-pull port pin has a schmitt triggered input that also has a glitch suppression circuit. the p89lpc970/971/972 device has high current source on eight pins in push-pull mode. see table 10 ? limiting values ? . 7.16.2 port 0 analog functions the p89lpc970/971/972 incorporates two analog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. digital outputs are disabled by putting the port output into the input-only (high-impedance) mode. digital inputs on port 0 may be disabled through the use of the pt0ad register, bits 1:5. on any reset, pt0ad[1:5] defaults to logic 0s to enable digital functions. 7.16.3 additional port features after power-up, all pins are in input-only mode. please note that this is different from the lpc76x series of devices. ? after power-up, all i/o pins except p1.5, may be configured by software. ? pin p1.5 is input only. pins p1.2 and p1.3 are configurable for either input-only or open-drain. every output on the p89lpc970/971/972 has bee n designed to sink typical led drive current. however, there is a maximum total output current for all ports which must not be exceeded. please refer to ta b l e 11 ? static characteristics ? for detailed specifications. all ports pins that can function as an output ha ve slew rate controlled outputs to limit noise generated by quickly switching output sig nals. the slew rate is factory-set to approximately 10 ns rise and fall times. 7.16.4 pin remap this feature allows the functions of uart /i2c/spi to be remapped to other pins. configuration register controls the multiplexe rs to allow connection between the pins and the on chip peripherals. see table 8 ? spi/i2c/uart pin remap ? . uart/i2c/spi, each has two options of pin co nfiguration: primary pin map and alternative pin map. after reset, uart/i2c/spi chooses the primary pin map as default. user can adjust to the alternative pin map through co nfiguring pincon regist er according to the application. please refer to p89lpc970/971/972 user manual for detail configurations.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 27 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.17 power management the p89lpc970/971/972 support a vari ety of power management features. power-on detect and brownout detect are desi gned to prevent incorrect operation during initial power-up and power loss or reduction during operation. the p89lpc970/971/972 support three different power reduction modes: idle mode, power-down mode, and total power-down mode. in addition, individual on-chip peripherals can be disabled to eliminat e unnecessary dynamic power use in any peripherals that are not re quired for the application. integrated pmu automatically adjusts internal regulators to minimize power consumption during idle mode, power-down mode and total power-down mode. in addition, the power consumption can be further reduced in normal or idle mode through configuring regulators mode according to the applications. 7.17.1 brownout detection the brownout detect function determines if the power supply voltage drops below a certain level. enhanced brownout detection has 3 independent functions: bod reset, bod interrupt and bod flash. these three functions are disabled in power-down mode and total power-down mode. in normal or idle mode, bod reset and bod flash are always on and can not be disabled in software. bod interrupt may be enabled or disabled in software. bod reset and bod interrupt, each has 6 leve ls. boe0 to boe2 (ucfg1[3:5]) are used as trip point configuration bits of bod re set. boicfg0 to boicfg2 in register bodcfg are used as trip point configuration bits of bod interrupt. bod reset voltage should be lo wer than bod interr upt trip point. bod flash is used for flash programming/erase protection and has only 1 trip point at 2.4 v. please refer to p89lpc970/971/972 user manual for detail configurations. if brownout detection works, the br ownout condition occurs when v dd falls below the brownout falling trip volt age and is negated when v dd rises above the brownout rising trip voltage. for correct activation of brownout detect, the v dd rise and fall times must be observed. please see ta b l e 11 ? static characteristics ? for specifications. table 8. spi/i2c/uart pin remap peripherals function primary pin out alternative pin out spi spiclk - p0.0 mosi - p1.7 miso - p1.6 ss -p1.4 i2c sda p1.3 - scl p1.2 - uart txd p1.0 - rxd p1.1 -
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 28 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.17.2 power-on detection the power-on detect has a function similar to the brownout detect, bu t is designed to work as power comes up initially to ensure that the device is reset from power-on. the pof flag in the rstsrc register is set to indicate an initial power-up co ndition. the pof flag will remain set until cleared by software. 7.17.3 power reduction modes the p89lpc970/971/972 supports three different power reduction modes. these modes are idle mode, power-down mode, and total power-down mode. 7.17.3.1 idle mode idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled in terrupt source or reset may terminate idle mode. 7.17.3.2 power-down mode the power-down mode stops th e oscillator in order to mi nimize power consumption. brownout detection circuitry is disabled. the p89lpc970/971/972 exits power-down mode via any reset, or certain interrupts. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include: brownout detect, watchdog timer, comparators and rtc/system timer (note that watchdog timer, comparators and rtc/system timer can be powered down separately). the internal rc oscillator is disabled unless bo th the rc oscillator has been se lected as the system clock and the rtc is enabled. 7.17.3.3 total power-down mode the total power-down mode is a deeper power reduction mode. brownout detection circuitry and analog comparators are disabl ed, as well as the internal rc oscillator. please use an external low frequency clock or 25 khz watchdog osc illator to achieve low power with the rtc runn ing during power-down. 7.17.4 regulators internal regulators can be adjusted automatically to minimize power consumption during different power reduction modes. in normal or idle modes, power consumption can be further reduced by configuring pmucon register. in normal or idle mode, regulators have two operation modes: high-speed mode and low current mode. the regulators can be configured to low curr ent mode to reduce the power consumption. after power-on-reset, internal regulators enter into high-speed mode as default. pmucon register is used to configure the regulators operation modes. lpmod bit is used to select the regulator?s mode and hco k bit indicates whether the switch completed or not. when switching back to high speed mode, first clear lpmod bit to select high speed mode, then check hcok bit. if hcok bit turns to ?1?, it means the switch was completed.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 29 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.18 reset the p1.5/rst pin can function as either a low-active reset input or as a digital input, p1.5. the reset pin enable (rpe) bit in ucfg1, when set to logic 1, enables the external reset input function on p1.5. when cleared, p1.5 may be used as an input pin. remark: during a power-up sequence, the rpe selection is overridden and this pin always functions as a reset input. an external circuit connected to this pin should not hold this pin low during a power-on sequence as this will keep the device in reset. after power-up this pin will fu nction as defined by the rpe bit. only a power-up reset will temporarily override the selection defined by rpe bit. other sources of reset will not override the rpe bit. reset can be triggered from the following sources: ? external reset pin (during power-up or if user configured via ucfg1) ? power-on detect ? brownout detect ? watchdog timer ? software reset ? uart break character detect reset for every reset source, there is a flag in the reset register, rstsrc. the user can read this register to determine the most recent re set source. these flag bits can be cleared in software by writing a logic 0 to the corresponding bit. more than one flag bit may be set: ? during a power-on reset, both pof and bof are set but the other flag bits are cleared. ? a watchdog reset is similar to a power-on reset, both pof and bof are set but the other flag bits are cleared. ? for any other reset, previously set flag bits that have no t been cleared will remain set. 7.18.1 reset vector following reset, the p89lpc970/ 971/972 will fetch instructions from either address 0000h or the boot address. the boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00h. the boot address will be used if a uart break reset oc curs, or the non -volatile boot status bit (bootstat.0) = 1, or the device is forced into isp mode during power-on (see p89lpc970/971/972 user manual ). otherwise, instructions will be fetched from address 0000h. 7.19 timers/counters 0 and 1 the p89lpc970/971/972 has two general purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. both can be configured to operate either as timers or event counters. an option to automatically toggle the t0 or t1 pins upon timer overflow has been added. in the ?timer? function, the register is incremented ev ery machine cycle.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 30 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core in the ?counter? function, the register is increm ented in response to a 1-to-0 transition at its corresponding count input pin, t0 or t1. in this function, the count input is sampled once during every machine cycle. timer 0 and timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). modes 0, 1, 2 and 6 are the same for both timers/counters. mode 3 is different. 7.19.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. in this mode, the timer register is configured as a 13-bit register. mode 0 operation is the same for timer 0 and timer 1. 7.19.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register are used. 7.19.3 mode 2 mode 2 configures the timer register as an 8-bit counter with automatic reload. mode 2 operation is the same for timer 0 and timer 1. 7.19.3.1 mode 3 when timer 1 is in mode 3 it is stopped. timer 0 in mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. when timer 1 is in mode 3 it can still be used by the se rial port as a baud rate generator. 7.19.3.2 mode 6 in this mode, the corresponding timer can be changed to a pwm with a full period of 256 timer clocks. 7.19.4 timer overflow toggle output timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. the same device pins that ar e used for the t0 and t1 count inputs are also used for the timer toggle outputs. the port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. 7.20 timers/counters 2, 3 and 4 the p89lpc970/971/972 has three external 16-bit timer/counters. all can be configured to operate either as timers or event counters. an option to automatically toggle pin tx (x = 2, 3 or 4) upon timer overflow has been added. in the ?timer? function, the register is incremented every pclk. in the ?counter? function, the register is increm ented in response to a 1-to-0 transition at its corresponding count input pin (t2/t3 /t4). in this function, the count input is sampled once during every machine cycle. only external timer 2/3/4 has the external input pin txex (x = 2, 3 or 4). a 1-to-0 transition on this pin can trigger a reload or capture event. timer 2, timer 3 and timer 4 have three operating modes (modes 0, 1 and 2).
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 31 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.20.1 mode 0: 16-bit timer/counter with auto-reload mode 0 configures the timer register as an 16 -bit timer/counter with automatic reload. an overflow upon the timer or a 1-to-0 transiti on at txex pin can cause the reload event. 7.20.2 mode 1: 16-bit timer/counter with input capture mode 1 configures the timer register as an 16-bit timer/counter with input capture. a 1-to-0 transition at txex pin can cause the capture event. 7.20.3 mode 2: 16-bit pwm mode in this mode, the corresponding timer can be changed to a 16-bit pwm generator with adjustable duty cycle. in this mode, the corresponding timer can be changed to a 16-bit pwm generator with adjustable duty cycle and adjustable full period (from 0, theoretically, to 131072). 7.20.4 timer overflow toggle output timers 2, 3 and 4 can be configured to auto matically toggle a port output whenever a timer overflow occurs. the same device pins that are used for the t2, t3 and t4 count inputs are also used for the ti mer toggle outputs. the port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. 7.21 rtc/system timer the p89lpc970/971/972 has a simple rtc that allows a user to continue running an accurate timer while the rest of the device is powered down. the rtc can be a wake-up or an interrupt source. the rtc is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loada ble down counter. when it reaches all logic 0 s, the counter will be reloaded again and the rtcf flag will be set. the clock source for this counter can be either the cpu clock (cclk) or the xtal oscillator. only powe r-on reset and watchdog reset will reset the rtc and its asso ciated sfrs to the default state. the 16-bit loadable counter portion of the rtc is readable by reading the rtcdatl and rtcdath registers. 7.22 uart the p89lpc970/971/972 has an enhanced uart that is compatible with the conventional 80c51 uart except that time r 2 overflow cannot be used as a baud rate source. the p89lpc970/971/972 does include an independent baud rate generator. the baud rate can be selected from the oscillator (divid ed by a constant), timer 1 overflow, or the independent baud rate generator. in addition to the baud rate generation, enhancements over the standard 80c51 uart include framing error detection, automatic address recognition, selectable doubl e buffering and several interrupt options. the uart can be operated in four modes: shift register, 8-bit uart, 9-bit uart, and cpu clock/32 or cpu clock/16. 7.22.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb first. the baud rate is fixed at 1 16 of the cpu clock frequency.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 32 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.22.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), and a stop bit (logic 1) . when data is received, the stop bit is stored in rb8 in special function register scon. th e baud rate is variable and is determined by the timer 1 overflow rate or the baud rate generator (described in section 7.22.5 ? baud rate generator and selection ? ). 7.22.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (logic 1). when data is transmitted, the 9 th data bit (tb8 in scon) can be assigned the value of logic 0 or logic 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9 th data bit goes into rb8 in special function register scon, while the stop bit is not saved. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 7.22.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 overflow rate or the baud rate generator (described in section 7.22.5 ? baud rate generator and selection ? ). 7.22.5 baud rate generator and selection the p89lpc970/971/972 enhanced uart has an independent baud rate generator. the baud rate is determined by a baud-rate preprogrammed into the brgr1 and brgr0 sfrs which together form a 16-bit baud rate divisor value that works in a similar manner as timer 1 but is much more accurate. if the baud rate generator is used, timer 1 can be used for other timing functions. the uart can use either timer 1 or the baud rate generator output (see figure 7 ). note that timer t1 is further divided by 2 if the smod1 bit (pcon.7) is cleared. the independent baud rate generators use oscclk. 7.22.6 framing error framing error is reported in the status regist er (sstat). in addition, if smod0 (pcon.6) is logic 1, framing errors can be made available in scon.7 respectively. if smod0 is logic 0, scon.7 is sm0. it is recommended that sm0 and sm1 (scon.7:6) are set up when smod0 is logic 0. fig 7. baud rate sources for uart (modes 1, 3) baud rate modes 1 and 3 sbrgs = 1 sbrgs = 0 smod1 = 0 smod1 = 1 timer 1 overflow (pclk-based) baud rate generator (cclk-based) 002aaa89 7 2
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 33 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.22.7 break detect break detect is reported in the status re gister (sstat). a break is detected when 11 consecutive bits are sensed low. the brea k detect can be used to reset the device and force the device into isp mode. 7.22.8 double buffering the uart has a transmit double buffer that allo ws buffering of the next character to be written to snbuf while the first character is being transmitted. doub le buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written be tween the start bit and the stop bit of the previous character. double buffering can be disabled. if disabl ed (dbmod, i.e., sstat.7 = 0), the uart is compatible with the conventio nal 80c51 uart. if enabled, t he uart allows writing to sbuf while the previous data is being shifted out. double buffering is only allowed in modes 1, 2 and 3. when operated in mode 0, double buffering must be disabled (dbmod = 0). 7.22.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) unlike the conventional uart, in double buffering mode, the ti interrupt is generated when the double buffer is ready to receive new data. 7.22.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) if double buffering is disabled tb8 can be written before or after sbuf is written, as long as tb8 is updated some time before that bit is shifted out. tb8 must not be changed until the bit is shifted out, as in dicated by the ti interrupt. if double buffering is enabled, tb must be updated before sbuf is written, as tb8 will be double-buffered together with sbuf data. 7.23 i 2 c-bus serial interface the i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bidirectional data transfer between masters and slaves ? multi master bus (no central master) ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus configuration is shown in figure 8 . the p89lpc970/971/972 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 34 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core fig 8. i 2 c-bus configuration other device with i 2 c-bus interface sda scl r p r p other device with i 2 c-bus interface p1.3/sda p1.2/scl p89lpc970/971/972 i 2 c-bus 002aaf092
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 35 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core fig 9. i 2 c-bus serial interface block diagram internal bus 002aaa8 99 address register comparator shift register 8 i2adr ack bit counter / arbitration and sync logic 8 i2dat timing and control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1.3 p1.3/sda p1.2/scl p1.2 timer 1 overflow control registers and scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 36 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.24 spi (pin remap) the p89lpc970/971/972 provides another high -speed serial communication interface: the spi interface. spi is a full-duplex, high-speed, synchronous communication bus with two operation modes: master mode and slave mode. up to 3 mbit/s can be supported in either master mode or slave mode. it has a transfer co mpletion flag and write collision flag protection. the spi interface has four pins: spiclk, mosi, miso and ss : ? spiclk, mosi and miso are typically ti ed together between two or more spi devices. data flows from master to slave on mosi (master out slave in) pin and flows from slave to master on miso (master in sl ave out) pin. the spic lk signal is output in the master mode and is input in the slave mode. if the spi system is disabled, i.e., spen (spctl.6) = 0 (res et value), these pins are co nfigured for port functions. ? ss is the optional slave select pin. in a ty pical configuration, an spi master asserts one of its port pins to select one spi devi ce as the current slav e. an spi slave device uses its ss pin to determine whether it is selected. typical connections are shown in figure 11 through figure 13 . fig 10. spi block diagram 002aaf091 cpu clock divider by 4, 16, 64, 128 select clock logic spi control register read data buffer 8-bit shift register spi control spi status register spr1 spif wcol spr0 spi clock (master) pin control logic s m s m m s miso p1.6 mosi p1.7 spiclk p0.0 ss p1.4 spi interrupt request internal data bus ssig spen spen mstr dord mstr cpha cpol spr1 spr0 mstr spen clock
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 37 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.24.1 typical spi configurations fig 11. spi single master single slave configuration fig 12. spi dual device configuration, where either can be a master or a slave 002aaa9 01 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port miso mosi spiclk ss 002aaa9 02 master slave 8-bit shift register spi clock generator spi clock generator 8-bit shift register miso mosi spiclk miso mosi spiclk ss ss
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 38 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.25 analog comparators two analog comparators are provided on the p89lpc970/971/97 2. input and output options allow use of the comparators in a num ber of different configurations. comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be configured to cause an interrupt when the output value changes. the overall connections to both comparators are shown in figure 14 . the comparators function to v dd =2.4v. when each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 s. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. when a comparator is disabled the comparator?s output, con, goes high. if the comparator output was low and then is disabled, the resulting transition of the comparator output from a lo w to high state will set the co mparator flag, cmfn. this will cause an interrupt if the comparator interrupt is enabled. the user should therefore disable the comparator interrupt prior to disabling the comparator. additionally, the user should clear the comparator flag, cmfn, after disabling the comparator. fig 13. spi single master multiple slaves configuration 002aaa9 03 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port port miso mosi spiclk ss slave 8-bit shift register miso mosi spiclk ss
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 39 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.25.1 selectable internal reference voltage an internal reference voltage generator may be used to supply a default reference when a single comparator input pin is used. the user may program one of eight different values for the internal reference voltage using the comparator reference register (cmpref). each of the two comparators may use a different reference voltage. 7.25.2 comparator interrupt each comparator has an interrupt flag contained in its configuration register. this flag is set whenever the comparator output changes st ate. the flag may be polled by software or may be used to generate an interrupt. the two comparators use one common interrupt vector. if both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determi ne which comparator caused the interrupt. 7.25.3 comparators and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated, but both comparators are disabled automatically in total power-down mode. if a comparator interrupt is enabled (except in total power-down mode), a change of the comparator output state will generate an in terrupt and wa ke-up the processor. if the comparator output to a pin is enabled, the pin should be conf igured in the push-pull mode in order to obtain fast switch ing times while in power-down mo de. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact sh ould be taken into account when system power consumption is an issue. to minimize power consumption, the user can disable the comparators via pcona.5, or put the device in total power-down mode. (1) see section 7.25.1 for more details. fig 14. comparator input and output connections comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref(cmp) (1) oe1 change detect co1 cmf1 interrupt 002aac346 cmp1 (p0.6) ec change detect cmf2 comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 40 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.26 kbi the keypad interrupt function (kbi) is intended primarily to allow a single interrupt to be generated when port 0 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. the port can be configured via sfrs for different tasks. the keypad interrupt mask re gister (kbmask) is used to define which input pins connected to port 0 can trigger the interrupt. the keypad pattern register (kbpatn) is used to define a pattern that is compared to the value of port 0. the keypad interrupt flag (kbif) in the keypad interrup t control register (kbcon) is set when the condition is matched while the keypad interrupt function is active. an interrup t will be generated if enabled. the patn_sel bit in the keypad in terrupt control register (kbcon) is used to define equal or not-equal for the comparison. in order to use the keypad interrupt as an original kbi function like in p87lpc76x series, the user needs to set kbpatn = 0ffh and patn_sel = 1 (not equal), then any key connected to port 0 which is enabled by th e kbmask register will caus e the hardware to set kbif and generate an interrupt if it has been enabled. the interrupt may be used to wake-up the cpu from id le or power-down modes. this feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. in order to set the flag and cause an interrupt, the pattern on port 0 must be held longer than six cclks. 7.27 watchdog timer the watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching it s terminal count. it consists of a programmable 12-bit prescaler, and an 8-bit down counter. the down counter is decremented by a tap taken from the prescaler. the clock source for the prescaler can be the pclk, the nominal 400 khz/25 khz watchdog oscillato r or low speed crystal osc illator. the wa tchdog timer can only be reset by a power-on reset. when the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. figure 15 shows the watchdog timer in watchdog mode. feeding the watchdog r equires a two-byte sequence. if pclk is selected as the watchdog clock and the cpu is powered down, the watchdog is disabled. the watchdog timer has a time-out period that ranges from a few s to a few seconds. please refer to the p89lpc970/971/972 user manual for more details.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 41 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.28 additional features 7.28.1 software reset the srst bit in auxr1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. care should be taken when writing to auxr1 to avoid accidental software resets. 7.28.2 dual data pointers the dual data pointers (dptr) provides tw o different data poin ters to specify the address used with certain instructions. the d ps bit in the auxr1 register selects one of the two data pointers. bit 2 of auxr1 is pe rmanently wired as a logic 0 so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibilit y of inadvertently altering other bits in the register. 7.29 flash program memory 7.29.1 general description the p89lpc970/971/972 flash memory provides in-circuit electrical erasure and programming. the flash can be erased, read, and written as bytes. the sector and page erase functions can erase any flash sector (1 kb) or page (64 bytes). the chip erase operation will erase t he entire program me mory. icp using standard commercial programmers is available. in addition, iap and byte-erase allows code memory to be used for non-volatile data storage. on-chip erase and write timing generation contribute to a user-friendly programming interface. the p89lpc970/971/972 flash reliably stores memory contents even after 100000 erase and program cycles. the cell is designed to (1) watchdog reset can also be caused by an in valid feed sequence, or by writing to wd con not immediately followed by a feed sequence. fig 15. watchdog timer in watchdog mode (wdte = 1) pre2 pre1 pre0 - - wdrun wdtof wdclk wdcon (a7h) shadow register prescaler 002aae542 8-bit down counter wdl (c1h) watchdog oscillator 400 khz oscillator 25 khz oscillator crystal oscillator pclk xtalwd (clkcon.4) wdmod (clkcon.5) 32 0 1 0 1 mov wfeed1, #0a5h mov wfeed2, #05ah reset (1) 0 1
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 42 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core optimize the erase and programming mech anisms. the p89lpc970/971/972 uses v dd as the supply voltage to perform the program/erase algorithms. when voltage supply is lower than 2.4 v, the bod flash is tripped and flash erase/program is blocked. 7.29.2 features ? programming and erase over the full operating voltage range. ? byte erase allows code memory to be used for data storage. ? read/programming/erase using isp/iap/icp. ? internal fixed boot rom, containing low-le vel iap routines available to user code. ? default loader providing isp via the serial port, located in upper end of user program memory. ? boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user. ? any flash program/erase operation in 2 ms. ? programming with industry-standard commercial programmers. ? programmable security for the code in the flash for each sector. ? 100000 typical erase/program cycles for each byte. ? 10 year minimum data retention. 7.29.3 flash organization the program memory consists of two/four/eight 1 kb sectors on the p89lpc970/971/972 device. each sector can be further divided into 64-byte pages. in addition to sector erase, page erase, and byte erase, a 64-byte page re gister is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. 7.29.4 using flash as data storage the flash code memory array of this devi ce supports individual byte erasing and programming. any byte in the code memory array may be read using the movc instruction, provided that the sector containing the byte has not been secured (a movc instruction is not allowed to read code memory contents of a secured sector). thus any byte in a non-secured sector may be used for non-volatile data storage. 7.29.5 flash programming and erasing four different methods of erasing or progra mming of the flash are available. the flash may be programmed or erased in the end-user application (iap) under control of the application?s firmware. another option is to use the icp mechanism. this icp system provides for programming through a serial clock/ serial data interface. as shipped from the factory, the upper 512 bytes of user code spac e contains a serial isp routine allowing for the device to be programmed in circuit thr ough the serial port. the flash may also be programmed or erased using a commercially available eprom programmer which supports this device. this device does not pr ovide for direct verifica tion of code memory contents. instead, this device provides a 32-bit crc result on either a sector or the entire user code space. remark: when voltage supply is lower than 2.4 v, the bod flash is tripped and flash erase/program is blocked.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 43 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 7.29.6 icp icp is performed without removing the microcont roller from the system. the icp facility consists of internal hardw are resources to facilitate remote programming of the p89lpc970/971/972 thro ugh a two-wire serial interfac e. the nxp icp facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of addi tional expense in components and circuit board area. the icp function uses five pins. only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. additional details may be found in the p89lpc970/971/972 user manual . 7.29.7 iap iap is performed in the application under the control of the microcontroller?s firmware. the iap facility consists of inter nal hardware resource s to facilitate programming and erasing. the nxp iap has made in-application programming in an embedded application possible without additional components. two methods are available to accomplish iap. a set of predefined iap functions are provided in a boot rom and can be called through a common interface, pgm_mtp. several iap calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device id. these functions are selected by setting up the microcontroller?s registers before making a call to pgm_mtp at ff03h. the boot rom occupies the program memory space at the top of the address space from ff00h to feffh, thereby not conflicting with the user program memory space. in addition, iap operations can be accomplish ed through the use of f our sfrs consisting of a control/status register, a data register, and two address register s. additional details may be found in the p89lpc970/971/972 user manual . 7.29.8 isp isp is performed without remo ving the microcontroller from the system. the isp facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the p89lpc 970/971/972 through the serial port. this firmware is provided by nxp and embedd ed within each p89lpc970/971/972 device. the nxp isp facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses five pins (v dd , v ss , txd, rxd, and rst ). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. 7.29.9 power-on reset code execution the p89lpc970/971/972 contains two special flash elements: the boot vector and the boot status bit. following reset, the p89lpc 970/971/972 examines the contents of the boot status bit. if the boot status bit is set to zero, power-up execution starts at location 0000h, which is the normal start address of the user?s application code. when the boot status bit is set to a value other than zero, the contents of the boot vector are used as the high byte of the execution address and the low byte is set to 00h. ta b l e 9 shows the factory default boot vector sett ing for these devices. a factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform isp functions. this code can be erased by the user.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 44 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core remark: users who wish to use this loader should take precautions to avoid erasing the 1 kb sector that contains this bootloader. inst ead, the page erase function can be used to erase the first eight 64-byte pages located in this sector. a custom bootloader can be written with the boot vector set to the custom bootloader, if desired. 7.29.10 hardware activation of the bootloader the bootloader can also be executed by forcing the device into isp mode during a power-on sequence (see the p89lpc970/971/972 user manual for specific information). this has the same effect as having a non-zero status byte. this allows an application to be built that will normally execute user code but can be manually forced into isp operation. if the factory default setting for the boot is changed, it will no longer point to the factory pre-programmed isp bootloader code. after programming the flash, the status byte should be programmed to zero in order to allow execution of the user?s application code beginning at address 0000h. 7.30 user configuration bytes some user-configurable features of the p8 9lpc970/971/972 must be defined at power-up and therefore cannot be set by the program af ter start of execution. these features are configured through the use of the flash byte ucfg1 and ucfg2. please see the p89lpc970/971/972 user manual for additional details. 7.31 user sector security bytes there are four/eight user sector security bytes on the p89lpc970/971/972. each byte corresponds to one se ctor. please see the p89lpc970/971/972 user manual for additional details. table 9. default boot vector values and isp entry points device default boot vector default bootloader entry point default bootloader code range 1 kb sector range p89lpc970 07h 0700h 0600h to 07ffh 0400h to 07ffh p89lpc971 0fh 0f00h 0e00h to 1fffh 0c00h to 0fffh p89lpc972 1fh 1f00h 1e00h to 1fffh 1c00h to 1fffh
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 45 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 8. limiting values [1] the following applies to table 10 : a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over ambient temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. [2] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k series resistor. table 10. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit t amb(bias) bias ambient temperature ? 55 +125 c t stg storage temperature ? 65 +150 c i oh(i/o) high-level output current per input/output pin -20ma i ol(i/o) low-level output current per input/output pin -20ma i i/otot(max) maximum total input/output current - 100 ma v xtal crystal voltage on xtal1, xtal2 pins when xtal1/xtal2 is used as crystal input/output; with respect to v ss ? 0.5 +4.0 v on xtal1, xtal2 pins when xtal1/xtal2 is used as gpio; with respect to v ss ? 0.5 +5.5 v v n voltage on any other pin with respect to v ss -5.5v p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [2] ? 3000 +3000 v charged device model; all pins ? 700 +700 v
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 46 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core fig 16. frequency vs. supply voltage v dd (v) 002aaf00 5 system frequency (mhz) 3.0 18 12 3.3 5.5 3.6 2.4 2.7
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 47 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 9. static characteristics table 11. static characteristics v dd = 2.4 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit i dd(oper) operating supply current v dd = 2.4 v f osc = 12 mhz, high-speed mode of regulators [2] -6 7ma f osc = 12 mhz, low current mode of regulators [2] -5 6ma v dd = 3.3 v f osc = 12 mhz, high-speed mode of regulators [2] -9 10ma f osc = 12 mhz, low current mode of regulators [2] -7 8ma v dd = 5.5 v f osc = 12 mhz, high-speed mode of regulators [2] -1011ma f osc = 12 mhz, low current mode of regulators [2] -8 9ma f osc = 18 mhz, high-speed mode of regulators [2] -11 12ma i dd(idle) idle mode supply current v dd = 2.4 v f osc = 12 mhz, high-speed mode of regulators [2] -3.54.5ma f osc = 12 mhz, low current mode of regulators [2] -3 4ma v dd = 3.3 v f osc = 12 mhz, high-speed mode of regulators [2] -5 6ma f osc = 12 mhz, low current mode of regulators [2] -4 5ma v dd = 5.5 v f osc = 12 mhz, high-speed mode of regulators [2] -6 7ma f osc = 12 mhz, low current mode of regulators [2] -4 5ma f osc = 18 mhz, high-speed mode of regulators [2] -6.57.5ma i dd(pd) power-down mode supply current v dd = 2.4 v; voltage comparators powered down [3] -2835 a v dd = 3.3 v; voltage comparators powered down [3] -3240 a v dd = 5.5 v; voltage comparators powered down [3] -3845 a
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 48 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core i dd(tpd) total power-down mode supply current v dd =2.4v [3] -1 5 a v dd =3.3v [3] -1 5 a v dd =5.5v [3] -1 5 a (dv/dt) r rise rate of v dd ; to ensure power-on reset signal 5 - 5000 v/s (dv/dt) f fall rate of v dd -- 50mv/ s v por power-on reset voltage -- 0.5v v ddr data retention supply voltage 1.5 - - v v th(hl) high-low threshold voltage except scl, sda 0.22v dd 0.4v dd -v v il low-level input voltage scl, sda only ? 0.5 - 0.4v dd v v th(lh) low-high threshold voltage except scl, sda - 0.6v dd 0.7v dd v v ih high-level input voltage scl, sda only 0.55v dd -5.5v v hys hysteresis voltage port 1 - 0.2v dd -v v ol low-level output voltage i ol =20ma; v dd =2.4vto 5.5v all ports, all modes except high-z [4] -0.61.0v i ol =3.2ma; v dd = 2.4 v to 5.5 v all ports, all modes except high-z [4] -0.20.3v v oh high-level output voltage i oh = ? 20 a; v dd = 2.4 v to 5.5 v; all ports, quasi-bidirectional mode v dd ? 0.3 v dd ? 0.2 - v i oh = ? 3.2 ma; v dd = 2.4 v to 5.5 v; all ports, push-pull mode v dd ? 0.7 v dd ? 0.4 - v i oh = ? 10 ma; v dd = 2.4 v to 5.5 v; all ports, push-pull mode -v dd ? 0.5 - v v xtal crystal voltage on xtal1, xtal2 pins when xtal1/xtal2 is used as crystal input/output; with respect to v ss ? 0.5 - +4.0 v on xtal1, xtal2 pins when xtal1/xtal2 is used as gpio; with respect to v ss ? 0.5 - +5.5 v v n voltage on any other pin with respect to v ss [5] ? 0.5 - +5.5 v c iss input capacitance [6] - - 15 pf i il low-level input current v i =0.4v [7] -- ? 80 a i li input leakage current v i =v il , v ih , or v th(hl) [8] -- 1 a i thl high-low transition current all ports; v i = 1.5 v at v dd =5.5v [9] ? 30 - ? 450 a table 11. static characteristics ?continued v dd = 2.4 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 49 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core r rst_n(int) internal pull-up resistance on pin rst pin rst 30 - 120 k bod interrupt v trip trip voltage falling stage boicfg2, boicfg1, bo icfg0 = 010 2.45 - 2.65 v boicfg2, boicfg1, bo icfg0 = 011 2.75 - 2.95 v boicfg2, boicfg1, bo icfg0 = 100 2.90 - 3.10 v boicfg2, boicfg1, bo icfg0 = 101 3.35 - 3.55 v boicfg2, boicfg1, bo icfg0 = 110 4.10 - 4.30 v boicfg2, boicfg1, bo icfg0 = 111 4.25 - 4.45 v rising stage boicfg2, boicfg1, bo icfg0 = 010 2.60 - 2.80 v boicfg2, boicfg1, bo icfg0 = 011 2.90 - 3.10 v boicfg2, boicfg1, bo icfg0 = 100 3.05 - 3.25 v boicfg2, boicfg1, bo icfg0 = 101 3.50 - 3.70 v boicfg2, boicfg1, bo icfg0 = 110 4.15 - 4.35 v boicfg2, boicfg1, bo icfg0 = 111 4.35 - 4.55 v table 11. static characteristics ?continued v dd = 2.4 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 50 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core [1] typical ratings are not guaranteed. the va lues listed are at room temperature, 3 v. [2] the i dd(oper) and i dd(idle) specifications are measured using an external clock with the followi ng functions disabled: comparators, real-time clock, and watchdog timer. [3] the i dd(pd) and i dd(tpd) specification is measured us ing an external clock with the following f unctions disabled: comparators, real-time clock, brownout detect, and watchdog timer. [4] see section 8 ? limiting values ? for steady state (non-transient) limits on i ol or i oh . if i ol /i oh exceeds the test condition, v ol /v oh may exceed the related specification. [5] this specification can be applied to pins which have a/d input or analog comparator input functions when the pin is not bein g used for those analog functions. when the pin is being used as an analog i nput pin, the maximum voltage on the pin must be limited to 4. 0 v with respect to v ss . [6] pin capacitance is characterized but not tested. [7] measured with port in quasi-bidirectional mode. [8] measured with port in high-impedance mode. [9] port pins source a transition current when used in quasi-bidire ctional mode and externally driven from logic 1 to logic 0. thi s current is highest when v i is approximately 2 v. bod reset v trip trip voltage falling stage boe2, boe1, boe0 = 010 2.15 - 2.35 v boe2, boe1, boe0 = 011 2.45 - 2.65 v boe2, boe1, boe0 = 100 2.75 - 2.95 v boe2, boe1, boe0 = 101 3.05 - 3.25 v boe2, boe1, boe0 = 110 3.75 - 3.95 v boe2, boe1, boe0 = 111 3.95 - 4.15 v rising stage boe2, boe1, boe0 = 010 2.30 - 2.50 v boe2, boe1, boe0 = 011 2.60 - 2.80 v boe2, boe1, boe0 = 100 2.90 - 3.10 v boe2, boe1, boe0 = 101 3.20 - 3.40 v boe2, boe1, boe0 = 110 3.85 - 4.05 v boe2, boe1, boe0 = 111 4.05 - 4.25 v bod flash v trip trip voltage falling stage 2.30 - 2.55 v rising stage 2.40 - 2.65 v v ref(bg) band gap reference voltage 1.19 1.23 1.27 v tc bg band gap temperature coefficient -1020ppm/ c table 11. static characteristics ?continued v dd = 2.4 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 51 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 10. dynamic characteristics table 12. dynamic characteristics (12 mhz) v dd = 2.4 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =12mhz unit min max min max f osc(rc) internal rc oscillator frequency nominal f = 7.3728 mhz trimmed to 1% at t amb =25 c; clock doubler option = off (default) 7.189 7.557 7.189 7.557 mhz nominal f = 14.7456 mhz; clock doubler option = on, v dd = 2.7 v to 5.5 v 14.378 15.114 14.378 15.114 mhz f osc(wd) internal watchdog oscillator frequency 360 440 360 440 khz f osc oscillator frequency 0 12 - - mhz t cy(clk) clock cycle time see figure 17 83 - - - ns f clklp low-power select clock frequency 08--mhz glitch filter t gr glitch rejection time p1.5/rst pin - 50 - 50 ns any pin except p1.5/rst - 15 - 15 ns t sa signal acceptance time p1.5/rst pin 125 - 125 - ns any pin except p1.5/rst 50 - 50 - ns external clock t chcx clock high time see figure 17 33 t cy(clk) ? t clcx 33 - ns t clcx clock low time see figure 17 33 t cy(clk) ? t chcx 33 - ns t clch clock rise time see figure 17 -8-8ns t chcl clock fall time see figure 17 -8-8ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 18 16t cy(clk) - 1333 - ns t qvxh output data set-up to clock rising edge time see figure 18 13t cy(clk) - 1083 - ns t xhqx output data hold after clock rising edge time see figure 18 -t cy(clk) + 20 - 103 ns t xhdx input data hold after clock rising edge time see figure 18 -0-0ns t xhdv input data valid to clock rising edge time see figure 18 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk 6 02.0mhz master - cclk 4 -3.0mhz
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 52 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core [1] parameters are valid over operating tem perature range unless otherwise specified. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spicyc spi cycle time see figure 19 , 20 , 21 , 22 slave 6 cclk -500-ns master 4 cclk -333-ns t spilead spi enable lead time see figure 21 , 22 slave 250 - 250 - ns t spilag spi enable lag time see figure 21 , 22 slave 250 - 250 - ns t spiclkh spiclk high time see figure 19 , 20 , 21 , 22 master 2 cclk -165-ns slave 3 cclk -250-ns t spiclkl spiclk low time see figure 19 , 20 , 21 , 22 master 2 cclk -165-ns slave 3 cclk -250-ns t spidsu spi data set-up time see figure 19 , 20 , 21 , 22 master or slave 100 - 100 - ns t spidh spi data hold time see figure 19 , 20 , 21 , 22 master or slave 100 - 100 - ns t spia spi access time see figure 21 , 22 slave 0 120 0 120 ns t spidis spi disable time see figure 21 , 22 slave 0 240 - 240 ns t spidv spi enable to output data valid time see figure 19 , 20 , 21 , 22 slave - 240 - 240 ns master - 167 - 167 ns t spioh spi output data hold time see figure 19 , 20 , 21 , 22 0-0-ns t spir spi rise time see figure 19 , 20 , 21 , 22 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns t spif spi fall time see figure 19 , 20 , 21 , 22 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns table 12. dynamic characteristics (12 mhz) ?continued v dd = 2.4 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =12mhz unit min max min max
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 53 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core table 13. dynamic characteristics (18 mhz) v dd = 3.6 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =18mhz unit min max min max f osc(rc) internal rc oscillator frequency nominal f = 7.3728 mhz trimmed to 1% at t amb =25 c; clock doubler option = off (default) 7.189 7.557 7.189 7.557 mhz nominal f = 14.7456 mhz; clock doubler option = on 14.378 15.114 14.378 15.114 mhz f osc(wd) internal watchdog oscillator frequency 360 440 360 440 khz f osc oscillator frequency 0 18 - - mhz t cy(clk) clock cycle time see figure 17 55 - - - ns f clklp low-power select clock frequency 08--mhz glitch filter t gr glitch rejection time p1.5/rst pin - 50 - 50 ns any pin except p1.5/rst - 15 - 15 ns t sa signal acceptance time p1.5/rst pin 125 - 125 - ns any pin except p1.5/rst 50 - 50 - ns external clock t chcx clock high time see figure 17 22 t cy(clk) ? t clcx 22 - ns t clcx clock low time see figure 17 22 t cy(clk) ? t chcx 22 - ns t clch clock rise time see figure 17 -5-5ns t chcl clock fall time see figure 17 -5-5ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 18 16t cy(clk) - 888 - ns t qvxh output data set-up to clock rising edge time see figure 18 13t cy(clk) - 722 - ns t xhqx output data hold after clock rising edge time see figure 18 -t cy(clk) + 20 - 75 ns t xhdx input data hold after clock rising edge time see figure 18 -0-0ns t xhdv input data valid to clock rising edge time see figure 18 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk 6 03.0mhz master - cclk 4 -4.5mhz t spicyc spi cycle time see figure 19 , 20 , 21 , 22 slave 6 cclk - 333 - ns master 4 cclk - 222 - ns
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 54 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core [1] parameters are valid over operating tem perature range unless otherwise specified. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spilead spi enable lead time see figure 21 , 22 slave 250 - 250 - ns t spilag spi enable lag time see figure 21 , 22 slave 250 - 250 - ns t spiclkh spiclk high time see figure 19 , 20 , 21 , 22 slave 3 cclk - 167 - ns master 2 cclk -111-ns t spiclkl spiclk low time see figure 19 , 20 , 21 , 22 slave 3 cclk - 167 - ns master 2 cclk -111-ns t spidsu spi data set-up time see figure 19 , 20 , 21 , 22 master or slave 100 - 100 - ns t spidh spi data hold time see figure 19 , 20 , 21 , 22 master or slave 100 - 100 - ns t spia spi access time see figure 21 , 22 slave 0 80 0 80 ns t spidis spi disable time see figure 21 , 22 slave 0 160 - 160 ns t spidv spi enable to output data valid time see figure 19 , 20 , 21 , 22 slave - 160 - 160 ns master - 111 - 111 ns t spioh spi output data hold time see figure 19 , 20 , 21 , 22 0-0-ns t spir spi rise time see figure 19 , 20 , 21 , 22 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns t spif spi fall time see figure 19 , 20 , 21 , 22 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns table 13. dynamic characteristics (18 mhz) ?continued v dd = 3.6 v to 5.5 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =18mhz unit min max min max
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 55 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 10.1 waveforms fig 17. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 fig 18. shift register mode timing 0 1234567 valid valid valid valid valid valid valid valid t xlxl 002aaa906 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 19. spi master timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa908 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 56 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core fig 20. spi master timing (cpha = 1) t spicyc t spiclkl t spiclkl t spiclkh t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa909 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 21. spi slave timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl t spilead t spilag t spidsu t spidh t spidh t spidsu t spidsu t spif t spia t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spioh t spidv t spir t spir t spif t spif ss spiclk (cpol = 0) (input) 002aaa910 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 57 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 10.2 isp entry mode fig 22. spi slave timing (cpha = 1) 002aaa911 t spicyc t spiclkh t spiclkh t spiclkl t spilead t spiclkl t spilag t spidsu t spidsu t spidh t spidh t spif t spir t spir t spia t spioh t spioh t spioh t spidis slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spidv t spidv t spir t spif t spif ss spiclk (cpol = 0) (input) spiclk (cpol = 1) (input) miso (output) mosi (input) table 14. dynamic characteristics, isp entry mode v dd = 2.4 v to 5.5 v, unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ max unit t vr v dd active to rst active delay time pin p1.5/rst 50 - - s t rh rst high time pin p1.5/rst 1- 32 s t rl rst low time pin p1.5/rst 1- - s fig 23. isp entry waveform 002aaa912 v dd rst t rl t vr t rh
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 58 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 11. other characteristics 11.1 comparator electrical characteristics [1] this parameter is characterized, but not tested in production. table 15. comparator electrical characteristics v dd = 2.4 v to 5.5 v, unless otherwise specified. t amb = ? 40 cto+85 c for industrial applications, unless otherwise specified. symbol parameter conditions min typ max unit v io input offset voltage - - 10 mv v ic common-mode input voltage 0 - v dd ? 0.3 v cmrr common-mode rejection ratio [1] -- ? 50 db t res(tot) total response time - 250 500 ns t (ce-ov) chip enable to output valid time - - 10 s i li input leakage current 0 v < v i p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 59 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 12. package outline fig 24. tssop20 package outline (sot360-1) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360 -1 a max. 1.1
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 60 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core fig 25. dip20 package outline (sot146-1) unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot146-1 99-12-27 03-02-13 a min. a max. b z max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2 4.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.078 0.17 0.02 0.13 sc-603 ms-001 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 20 1 11 10 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) (1) dip20: plastic dual in-line package; 20 leads (300 mil) sot146 -1
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 61 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 13. abbreviations table 16. abbreviations acronym description ccu capture/compare unit cpu central processing unit crc cyclic redundancy check dac digital to analog converter eeprom electrically erasable programmable read-only memory emi electro-magnetic interference eprom erasable programmable read-only memory gpio general purpose input/output irc internal rc lsb least significant bit msb most significant bit pga programmable gain amplifier pll phase-locked loop pwm pulse width modulator ram random access memory rc resistance-capacitance rtc real-time clock sar successive approximation register sfr special function register spi serial peripheral interface uart universal asynchronous receiver/transmitter wdt watchdog timer
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 62 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 14. revision history table 17. revision history document id release date data sheet status change notice supersedes p89lpc97x v.3 20100608 product data sheet - p89lpc97x_2 modifications: ? section 7.4 ? crystal oscillator option ? on page 19 : updated text. ? section 7.27 ? watchdog timer ? on page 40 : updated text. p89lpc97x_2 20100427 product data sheet - p89lpc97x_1 modifications: ? changed data sheet status to ?product data sheet?. ? table 11 ?static characteristics?: updated mi n/typ/max values for bod interrupt and bod reset. ? table 11 ?static characteristics?: updated cond itions and min/max/unit values for (dv/dt) r . p89lpc97x_1 20091217 preliminary data sheet - -
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 63 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 64 of 66 nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
p89lpc97x all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 8 june 2010 65 of 66 continued >> nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 10 7.1 special function registers . . . . . . . . . . . . . . . . 10 7.2 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.1 clock definitions . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.2 cpu clock (oscclk). . . . . . . . . . . . . . . . . . . 19 7.4 crystal oscillator option. . . . . . . . . . . . . . . . . . 19 7.4.1 low speed oscillator option . . . . . . . . . . . . . . 19 7.4.2 medium speed oscillator option . . . . . . . . . . . 19 7.4.3 high speed oscillator option . . . . . . . . . . . . . . 19 7.5 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 on-chip rc oscillator option . . . . . . . . . . . . . . 20 7.7 watchdog oscillator option . . . . . . . . . . . . . . . 20 7.8 external clock input option . . . . . . . . . . . . . . . 20 7.9 clock source switching on the fly . . . . . . . . . . 20 7.10 cclk wake-up delay . . . . . . . . . . . . . . . . . . . 21 7.11 cclk modification: divm register . . . . . . . . . 21 7.12 low power select . . . . . . . . . . . . . . . . . . . . . . 21 7.13 memory organization . . . . . . . . . . . . . . . . . . . 22 7.14 data ram arrangement . . . . . . . . . . . . . . . . . 22 7.15 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15.1 external interrupt inputs . . . . . . . . . . . . . . . . . 23 7.16 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.16.1 port configurations . . . . . . . . . . . . . . . . . . . . . 25 7.16.1.1 quasi-bidirectional outp ut configuration . . . . . 25 7.16.1.2 open-drain output configuration . . . . . . . . . . . 25 7.16.1.3 input-only configuration . . . . . . . . . . . . . . . . . 26 7.16.1.4 push-pull output configuration . . . . . . . . . . . . 26 7.16.2 port 0 analog functions . . . . . . . . . . . . . . . . . . 26 7.16.3 additional port features. . . . . . . . . . . . . . . . . . 26 7.16.4 pin remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.17 power management . . . . . . . . . . . . . . . . . . . . 27 7.17.1 brownout detection . . . . . . . . . . . . . . . . . . . . . 27 7.17.2 power-on detection. . . . . . . . . . . . . . . . . . . . . 28 7.17.3 power reduction modes . . . . . . . . . . . . . . . . . 28 7.17.3.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.17.3.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 28 7.17.3.3 total power-down mode . . . . . . . . . . . . . . . . 28 7.17.4 regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.18 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.18.1 reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.19 timers/counters 0 and 1 . . . . . . . . . . . . . . . . 29 7.19.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.19.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.19.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.19.3.1 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.19.3.2 mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.19.4 timer overflow toggle output . . . . . . . . . . . . . 30 7.20 timers/counters 2, 3 and 4 . . . . . . . . . . . . . . 30 7.20.1 mode 0: 16-bit timer/counter with auto-reload. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.20.2 mode 1: 16-bit ti mer/counter with input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.20.3 mode 2: 16-bit pwm mode . . . . . . . . . . . . . . 31 7.20.4 timer overflow toggle output . . . . . . . . . . . . . 31 7.21 rtc/system timer . . . . . . . . . . . . . . . . . . . . . 31 7.22 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.22.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.22.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.22.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.22.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.22.5 baud rate generator and selection. . . . . . . . . 32 7.22.6 framing error . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.22.7 break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.22.8 double buffering. . . . . . . . . . . . . . . . . . . . . . . 33 7.22.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . 33 7.22.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . 33 7.23 i 2 c-bus serial interface. . . . . . . . . . . . . . . . . . 33 7.24 spi (pin remap) . . . . . . . . . . . . . . . . . . . . . . . 36 7.24.1 typical spi configurations . . . . . . . . . . . . . . . 37 7.25 analog comparators. . . . . . . . . . . . . . . . . . . . 38 7.25.1 selectable internal refe rence voltage. . . . . . . 39 7.25.2 comparator interrupt . . . . . . . . . . . . . . . . . . . 39 7.25.3 comparators and power reduction modes . . . 39 7.26 kbi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.27 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 40 7.28 additional features . . . . . . . . . . . . . . . . . . . . . 41 7.28.1 software reset . . . . . . . . . . . . . . . . . . . . . . . . 41 7.28.2 dual data pointers . . . . . . . . . . . . . . . . . . . . . 41 7.29 flash program memory . . . . . . . . . . . . . . . . . 41 7.29.1 general description . . . . . . . . . . . . . . . . . . . . 41 7.29.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
nxp semiconductors p89lpc970/971/972 8-bit microcontroller with accelerated two-clock 80c51 core ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 june 2010 document identifier: p89lpc97x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 7.29.3 flash organization . . . . . . . . . . . . . . . . . . . . . 42 7.29.4 using flash as data storage . . . . . . . . . . . . . . 42 7.29.5 flash programming and erasing . . . . . . . . . . . 42 7.29.6 icp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.29.7 iap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.29.8 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.29.9 power-on reset code execution . . . . . . . . . . . 43 7.29.10 hardware activation of the bootloader . . . . . . 44 7.30 user configuration bytes . . . . . . . . . . . . . . . . . 44 7.31 user sector security bytes . . . . . . . . . . . . . . . 44 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 45 9 static characteristics. . . . . . . . . . . . . . . . . . . . 47 10 dynamic characteristics . . . . . . . . . . . . . . . . . 51 10.1 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.2 isp entry mode . . . . . . . . . . . . . . . . . . . . . . . . 57 11 other characteristics . . . . . . . . . . . . . . . . . . . . 58 11.1 comparator electrical characteristics . . . . . . . 58 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 59 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 62 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 63 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 63 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 64 16 contact information. . . . . . . . . . . . . . . . . . . . . 64 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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